This is a guide for running simulations on virtuoso.


  1. Prepare simulation and synthesis results.
  2. Modify the netlist file generated by synthesis tool, whose path is workdir/syn/module_name/module_name.v.

a. Add the VDD and VSS ports, which should be inout type to every module.

b. Use replace tool to modify every cell’s port, add .VDD(VDD), .VSS(VSS), .VNW(VDD), .VPW(VSS).


  1. Run virituoso in the virtuoso directory.

    cd virtuoso/
    virtuoso &
  2. In library manager, File -> New -> Library -> New Library -> Name: lib_name Path: $ProjectPath/virtuoso/ -> OK.

  1. Attach to existing library -> lib_name -> OK.

  1. In log window, File -> import -> verilog -> netlist file -> OK. The Reference Library should be copied form the name in library manager. Other parameter is shown in the following figure.

  1. In library manager, File -> new -> cellview -> Name: lib_tb Viwe:functional Type:Verilog -> OK.

  1. In popup text editor, paste the testbench without tested module, also add output port to the testbench.

  1. In library manager, File -> new -> cellview -> Name: lib_top View:schematic -> OK.

  1. Display the schematic of the tested module, and add the testbench to the schematic

a. Add the instances, source and ground. Also, connect the ports. Instances source and ground can by created by Create -> Instance. The source and ground can be found in the analogLib library.

b. Give the voltage to the sources. Select the source, right click, and modify the DC Value in the Property Editor, the value should be vdd and vss.

c. Press l in the keyboard to add the label to the signals. Then click check and save.

  1. In library manager, File -> new -> cellview -> Name: lib_top View:config -> OK.

a. In popup window, View: schematic, use template ARM. Then, select the Library List, which should include own library and the library which is needed -> OK.

b. Select the cells in red, rignht click -> Set Multiple Views -> Specify SPICE Source File -> Corresponding.cdl file -> OK. The .cdl file should be found in the /cad/tech/ directory. Then, click Recompute the hierarchy -> OK.


  1. Click ADE Explorer -> Create New View to get the maestro cell view.

a. Setup -> Model Library. Select the .scs file in the /cad/tech/ directory, section should be tt.

b. Double click the Analyses to set stop time.

c. Setup -> Connect Rules.

d. Double click the Disign Variables, click Copy From to set the vdd and vss value.

e. Outputs -> TO Be Plotted -> Select On Design -> Select the output signals. Note that the sources should be selected, too.


  1. Run the simulation.
  2. If there is some error, check the log window. Open the functional view of corresponding cell, and click Bulid a database -> replace. Then, check the lib_top schematic. After that, run the simulation again.